1. Field of the Invention
The present invention relates to a method of fabricating an NMOS (n type metal-oxide-semiconductor) transistor.
2. Description of the Prior Art
Strained-Si scheme has become essential for 45 nm and beyond CMOS technology. For example, the embedded SiGe (eSiGe) is introduced into the S/D area to enhance PMOS performance, and, the embedded silicon carbide (eSiC) in the S/D area is for enhancing NMOS performance due to large tensile stress resulted from the smaller lattice constant of SiC. There are two different approaches to form the eSiC S/D. One is to recess S/D region and to grow SiC directly using selective epitaxy process. Another is to use carbon ion implantation to pre-amorphorize silicon in a source/drain region and solid phase epitaxy (SPE) anneal to form SiC in the S/D region. The resultant MOS structure is obtained as shown in FIG. 1. In which, the source/drain region 12 is formed through doping a dopant using a first spacer 14, a second spacer 16, and a gate structure 18 as a mask. SiC is formed after the source/drain region 12 is formed and accordingly mainly distributed within an upper portion 20 of the source/drain region 12 in a proximately uniform concentration as shown by a referral number 22.
However, the great increase of the sheet resistance (Rs) in doped SPE SiC will offset the performance gain obtained from the strain effect. Moreover, the high temperature thermal processes will induce carbon atom precipitation out from substitutional sites and reduce the channel stress.
Therefore, there is still a need for a novel method to fabricate an NMOS transistor having relatively high SiC concentration for increasing electron mobility while without increasing sheet resistance (Rs).